• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of detecting a buried defect in a non-destructive state immediately after completion of a high temperature spatter in which an Al-based alloy is embedded in a hole. An element formation region and an inspection pattern formation region are formed on the wafer, the wiring layer 3 is formed on the semiconductor substrate 1 and the insulating film 2, and the interlayer insulating film () is formed on the wiring layer 3 and the semiconductor substrate 1. 4), a first hole for exposing the wiring layer 3 in the interlayer insulating film 4 of the element formation region is formed, and the same as the first hole for exposing the semiconductor substrate 1 to the interlayer insulating film of the inspection pattern region. A second hole having a shape is formed, an Al-based alloy is embedded in the first and second holes, the second hole is observed, and whether or not voids are generated in the first hole.
    公开号:KR19980081493A
    申请号:KR1019980013729
    申请日:1998-04-17
    公开日:1998-11-25
    发明作者:아이자와가즈오
    申请人:가네코히사시；닛폰덴키(주)；
    IPC主号:
    专利说明:

    Manufacturing Method of Semiconductor Device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, when an Al-based alloy is buried in a hole using a high temperature process, a defect in the hole can be easily and shortly detected immediately after completion of the embedding process. It relates to a manufacturing method.
    With the miniaturization of semiconductor devices, the dimensions of the holes connecting the lower layer wirings and the upper layer wirings have also become smaller. Al-based alloys are usually used for lower and upper wirings, and the Al-based alloys are usually formed by a spatter method. As the size of holes increases and the aspect ratio of holes exceeds about 0.8, the step coverage of the Al-based alloy in the holes decreases and sometimes it is impossible to connect. The case occurs. As a result, the reliability of the wiring is lowered or a poor conduction occurs and the reliability of the device becomes a problem. Therefore, there is also a method of securing electrical connection by stacking Ti, TiN and the like having better step coverage than Al-based alloys before embedding the Al-based alloys, but the number of steps is increased.
    In order to solve this problem, several embedding methods for improving the step coverage of the Al-based alloy in the micropores have been proposed. The high temperature Al spatter which is one of the methods is demonstrated in process order using FIG. 5A, 5B, 5C.
    As shown in FIG. 5A, a first wiring layer 3 is formed on the Si substrate 1 and the insulating film 2 thereon. The interlayer insulating film 4 is formed on the first wiring layer 3 and the insulating film 2 by a CVD method, etc., and the through hole 5 is manufactured by performing a lithography process and a dry etching process on the interlayer insulating film 4. . Next, the Ti film 7 which is a material having good reactivity with the Al-based alloy is formed integrally on the interlayer insulating film 4 and in the through hole 5 (Fig. 5B), and then the Al-based alloy 14 in the same vacuum. Was first deposited by a spatter of about 1/3 to 1/2 of the desired film thickness at a low temperature of 150 ° C. or lower, and then the Al-based alloy 14 having the remaining film thickness was heated to a temperature of 400 to 500 ° C. It is possible to embed the Al-based alloy 14 in the hole by spattering in the state (Fig. 5C).
    By the way, in the method of embedding the Al-based alloy 14 in the through hole 5 with such a high-temperature spatter, sometimes a defective buried hole 15 having a void 12 is formed in the hole as shown in FIG. There is. Such a landfill defect is caused by a decrease in the degree of vacuum in the apparatus or a decrease in the heater temperature, resulting in a poor fluidity of the Al-based alloy 14 and an increase in the protruding shape, resulting in the Al-based alloy 14 blocking the opening. This is caused by the closing of the top of the hole in the beginning. If such defective buried holes 15 are generated, the result is a result of inducing a decrease in the reliability of wiring as in the case where the step coverage of the Al-based alloy in the holes is reduced. Therefore, void 12 of buried defects should not be generated in the hole. Alternatively, it is important to detect the presence of defective landfill even if it is generated. By the way, the presence or absence of defective filling is unknown even when the upper part is observed because the upper part is blocked by the Al-based alloy 14 as shown in FIG. For this reason, conventionally, it was necessary to confirm the presence of defective filling by cutting the wafer and SEM observation immediately after completion of filling. In this method, it is difficult to identify a large number of holes, it is virtually impossible to cut the product chip after the embedding process is completed, and it is difficult to cope with the actual product by the detection method using the wafer for monitor. However, there were some problems with the increased cost.
    In order to avoid this problem, a method of detecting a landfill defect of an Al-based alloy on a product in a non-destructive state has been proposed in Japanese Patent Laid-Open No. 6-69037. 7A and 7B show the method according to the drawing. 7A and 7B show a defect detection observation pattern in embedding an Al-based alloy into a contact hole at the same time as a product pattern on a wafer, and the base metal 71 is formed by Ti / to prevent Al from protruding out of the substrate. TiON / Ti structure. 7A shows a failure detection observation pattern after completion of the embedding process of the Al-based alloy. In a well-embedded hole 17, an Al-based alloy, here AlSi (18) and a reaction product Al-Si-Ti (19) with Ti on the upper layer of the base metal 71 are formed in the hole and the lower layer of the wiring. have. On the other hand, in the hole 20 in which the poor landfill is generated, the reaction product 19 is not produced in the hole and unreacted Ti remains. Next, the defect detection observation pattern is exposed by the lithography process, and only the Al-based alloy 18 is selectively removed by wet etching (Fig. 7B, after removing the Al-based alloy 18, the hole surface may be observed by SEM or the like. The Al-Si-Ti alloy 19 remaining in the buried hole 17 has a large surface unevenness, while the unreacted Ti remaining in the buried hole 20 has a smooth surface, and the difference between the two is determined as the surface shape. can do.
    According to this method, it is possible to detect the presence of defective landfill on the product even in the non-destructive state.
    However, the above method can detect a landfill defect on a product even in a non-destructive state. However, in order to detect a defect, a process of exposing only a detection pattern by a lithography process and etching of Al are required. There are disadvantages such as increase or increase in manufacturing cost. In addition, since it takes time until detection, even if defective landfilling is detected, there is a possibility that defective landfilling may spread to the product which has been embedded with Al during the detection and damage to manufacturing may be expanded. Such problems are problematic in that defective landfills cannot be detected immediately after Al embedding is performed.
    Accordingly, it is an object of the present application to provide a method for manufacturing a semiconductor device which can detect defective filling immediately and easily after the end of the high-temperature sputtering.
    The method for manufacturing a semiconductor device of the present invention comprises the steps of forming a wiring layer in the element formation region of a semiconductor wafer having an element formation region and an inspection pattern formation region, while not forming a wiring layer in the inspection pattern formation region, A step of forming an interlayer insulating film, and a first hole exposing a part of the wiring layer formed in the element formation region by selectively removing the interlayer insulating film and a second part exposing a portion of the silicon layer of the test pattern forming region. And a step of forming a hole and a step of embedding an Al-based alloy in the first and second holes.
    In the method for manufacturing a semiconductor device of the present invention, the first hole is formed as a plurality of first hole groups, and the second hole is formed as a plurality of second hole groups, and each hole of the first hole group is The size and spacing are characterized by being substantially the same as the size and spacing of the respective holes of the second group of holes.
    According to the present invention, when the Al-based alloy is well embedded in the second hole formed in the test pattern region, the silicon layer and Al cause mutual diffusion and a so-called spike phenomenon occurs. As a result, the upper portion of the hole is not flattened and Al is lost in the hole. There is also a wage. On the other hand, in the case where defective filling (void) occurs, since Al does not flow in the hole, Al and the silicon layer do not mutually diffuse and the upper part of the hole becomes flat. By observing the upper part of the second hole by SEM or the like, it is possible to detect a defective filling of the first hole in the element formation region immediately after the high-temperature spatter of the Al-based alloy is in a non-destructive state.
    1A to 1C are cross-sectional views for describing an embodiment of the present invention.
    2A to 2C are cross-sectional views for explaining embodiments of the present invention.
    3 is a cross-sectional view for explaining an embodiment of the present invention.
    4 is a cross-sectional view for explaining an embodiment of the present invention.
    5A to 5C are cross-sectional views for explaining an example of a method for embedding an Al-based alloy in a hole;
    FIG. 6 is a cross-sectional view showing defective embedding in a method of embedding an Al-based alloy in a hole; FIG.
    7A and 7B are cross-sectional views for explaining a conventional method for detecting defects in landfills.
    Explanation of symbols on the main parts of the drawings
    1 Si substrate 2 Insulation film
    3: first wiring layer 4: interlayer insulating film
    5 through hole 7 Ti
    8: AlCu 12: void
    14: Al-based alloy 18: AlSi
    19: Al-Si-Ti alloy 71: Ti / TiON / Ti
    90: Al-Cu-Ti Alloy
    Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings to clarify the above objects, features and advantages of the present invention.
    A first embodiment of the present invention will be described using Figs. 1A to 4.
    In Fig. 1, the left side shows the test pattern forming region, and the right side shows this pattern forming region.
    First, as shown in FIG. 1A, the first wiring layer 3 is formed on the Si substrate and the insulating film 2 thereon. The insulating film 2 is mainly composed of SiO 2 , but may include phosphorus, / * boron, or the like, and may be laminated and deposited. The first wiring layer 3 is composed of a laminated film of an Al-based alloy and a barrier metal including an anti-reflection film. For example, a TiN3a / Al-based alloy 3b / TiN3C / Ti3d is formed by a spatter method of about 500 to 800 nm in thickness. Form. Next, the first wiring layer 3 is patterned. At this time, the Si substrate 1 is exposed in the test pattern formation region. Subsequently, an interlayer insulating film 4 is formed on the first wiring layer 3 and the insulating film 2 in this pattern region on the Si substrate 1 in the inspection pattern region by a CVD method or the like. This interlayer insulating film 4 is planarized using a coating film, chemical mechanical polishing, or the like (FIG. 1B). Thereafter, a lithography process and a dry etching process are performed on the interlayer insulating film 4 in both pattern forming regions, and as shown in FIG. 1C, the through holes 5 are formed in the pattern forming region, and the pattern seen in the inspection pattern forming region. The hole 6 of the same shape is opened. The inspection pattern forming region is formed so as to be provided at one or more places in the wafer, for example, at the center of the wafer, at four edges, or the like as shown in FIG. In addition, a plurality of holes are provided in one inspection pattern, and not only the shape but also the intervals between the holes are made equal to this pattern. In particular, among the various hole patterns of the present pattern, an inspection pattern equivalent to a pattern that is likely to cause poor filling may be provided.
    Next, Ti (7) is formed as a film on both patterns by the spatter method as a base metal for improving the wettability of Al (FIG. 2A). Ti (7) has a thickness (about 20 to 50 nm) in which the Al-based alloy embedding process, in which Ti at the bottom of the hole is continuously divided into two stages, reacts with the Al-based alloy spattered in the first stage. Form.
    Thereafter, in the same vacuum, AlCu (8) as Al-based alloy and the temperature at which Al does not agglomerate at a thickness (about 200 to 400 nm) in which all of the Ti (7) at the bottom of the hole become an alloy layer with AlCu (usually in the same vacuum). Film is formed on both patterns). The spatter at this time is performed at a rate of about 1000 nm / min. Since Ti (7) is formed on the insulating film 4 slightly thicker than in the hole in FIG. 2A, Ti, which is not an alloy layer, remains. Both patterns have the same shape in this step. Next, the spatter rate is about 100 to 200 nm at a temperature (a wafer temperature is in the range of about 400 to 450 ° C.) at which the fluidity becomes good for the remaining AlCu (8) having a desired film thickness (about 600 to 800 nm) in the same vacuum. Slow to about / min to form a film on both patterns.
    As shown in Fig. 2C, when AlCu 8 flows before the AlCu 8 is clogged in the upper portion of the pattern, AlCu 8 is deposited in the through hole 5. As a result, a well-filled hole 9 is formed. By the way, when AlCu 8 is clogged in the upper part of the hole and AlCu 8 does not flow in the hole 5, a hole 10 is formed having a void 12 which causes defective filling. The surface of the AlCu 8 is planarized in both the hole 10 and the hole 9 having poor filling, and there is no detectable defect in the upper portion.
    On the other hand, in the inspection pattern, when AlCu (8) is not blocked at the top of the hole, that is, in this pattern, when it is obtained in a good landfill such as the hole 9, AlCu (8) which has flowed to the bottom of the hole and the empty Al-Cu-Ti Reacts with the alloy layer 9 and also with the underlying Si substrate 1. At this time, AlCu 8 diffuses in the Si substrate 1 and forms a spike 21 in the Si substrate. The formation of the spikes 21 reduces AlCu 8 that has flowed in the hole. As a result, AlCu disappears in the hole 11 of the inspection pattern which is well buried when the AlCu 8 reaches the predetermined film thickness. Alternatively, recesses occur as shown in FIG. 3. On the other hand, when AlCu (8) is blocked in the upper part of the hole, that is, when a poor filling such as the hole 10 occurs in this pattern, AlCu (8) and Al do not flow in the bottom of the hole even in the inspection pattern. Reaction with -Cu-Ti and Si substrates does not occur. As a result, the hole 13 of the inspection pattern in which the AlCu 8 is flattened in the upper portion of the hole and the voids 12 are generated is poorly embedded.
    By observing the hole of the inspection pattern thus formed by SEM or the like from the top, it can be judged that if there is a dent in the hole, if it is flattened, it is a poor filling. Therefore, it is possible to inspect the presence or absence of defective landfilling easily and shortly after completion of the landfilling process.
    Here, in order to improve adhesion of the Al-based alloy to the inner wall of the hole and to fill the hole satisfactorily, the Al-based alloy is deposited at a low temperature (temperature at which Al does not agglomerate) and at a high temperature (the fluidity of Al is improved. Temperature). The same effect occurs even if the formation of this two-stage film is performed in the same film forming chamber or in another film forming chamber. In the same film formation chamber, the film formation of 300 ° C. or lower is realized by setting the heating step so that the wafer temperature is 400 to 450 ° C., but preventing gas from flowing behind the wafer. The spatter power is set to about 100 nm / min. Thereafter, gas is flowed from the back surface of the wafer to form a film at 400 to 450 占 폚. The spatter power is set to be about 100 to 200 nm / min.
    The method of embedding Al is not limited to the silver spatter method, and may be any method as long as Al is flowed at a high temperature such as a reflow method or a high pressure spatter method.
    In this embodiment, AlCu is used as the Al-based alloy, but may contain other elements such as Si and Ge. Moreover, although Al type alloy was used for base wiring, high melting metal wiring, for example, W may be sufficient.
    In this embodiment, the holes of the inspection pattern are formed on the Si substrate, but not limited thereto. For example, the holes may be formed on the polysilicon of the memory capacitor.
    As described above, according to the present invention, by forming the same inspection pattern on the product wafer, the formation of Al-based wiring by high-temperature spatter or the like, in particular, the detection of Al defective filling is performed in a non-destructive state and after the embedding process. It is possible to provide a method for manufacturing a semiconductor device that can be readily and immediately performed in a short time. As a result, it is possible to prevent an increase in defective products produced during the reduction or detection of the reference wafer, and the manufacturing cost can be reduced. Moreover, since the inspection pattern is the same as this pattern, the effect that the inspection precision of the presence or absence of defective filling is improved is also acquired.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] In the manufacturing method of a semiconductor device,
    Forming a wiring layer in the element formation region of the semiconductor wafer having the element formation region and the inspection pattern formation region while not forming a wiring layer in the inspection pattern formation region;
    Forming an interlayer insulating film on the entire surface;
    Forming a first hole for exposing a portion of the wiring layer formed in the element formation region and a second hole for exposing a portion of the silicon layer of the test pattern formation region by selectively removing the interlayer insulating film;
    And a step of embedding the Al-based alloy in the first and second holes.
    [2" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 1, wherein the inspection pattern forming region is provided in a plurality of places including a center of the semiconductor wafer.
    [3" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 1, wherein the wiring layer is Al wiring or W wiring.
    [4" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 1, wherein the silicon layer is a single crystal silicon substrate or a polysilicon layer.
    [5" claim-type="Currently amended] The method according to any one of claims 1 to 4, further comprising a step of observing the second hole in the test pattern forming region after embedding an Al-based alloy in the first and second holes,
    Thereby, a method of manufacturing a semiconductor device characterized by checking whether voids are generated in the first hole of the element formation region.
    [6" claim-type="Currently amended] The said 1st hole is formed as a some 1st group of holes, The said 1st hole of any one of Claims 1-4.
    The second hole is formed as a plurality of second hole groups,
    The size and spacing of each hole of the first hole group is substantially the same as the size and spacing of each hole of the second hole group.
    类似技术:
    公开号 | 公开日 | 专利标题
    KR101344146B1|2013-12-23|A semiconductor device and a method of manufacturing the same
    JP4832807B2|2011-12-07|Semiconductor device
    KR100400037B1|2003-09-29|Semiconductor device with contact plug and method for manufacturing the same
    US4926237A|1990-05-15|Device metallization, device and method
    US6531783B1|2003-03-11|Method of via formation for multilevel interconnect integrated circuits
    DE69836114T2|2007-04-19|Copper wiring with improved electromigration resistance and reduced defect sensitivity
    CN101390204B|2011-03-30|Novel structure and method for metal integration
    US7807567B2|2010-10-05|Semiconductor device with interconnection structure for reducing stress migration
    KR100212614B1|1999-08-02|Semiconductor device and manufacturing method thereof
    JP4113263B2|2008-07-09|Structure and method for forming an enlarged head portion of a plug for removing surrounding conditions
    US7122462B2|2006-10-17|Back end interconnect with a shaped interface
    US6881666B2|2005-04-19|Method of fabricating semiconductor device
    US8658534B2|2014-02-25|Method for producing a semiconductor component, and semiconductor component
    US6806579B2|2004-10-19|Robust via structure and method
    US4619037A|1986-10-28|Method of manufacturing a semiconductor device
    CN1106688C|2003-04-23|A novel via hole profile and method of fabrication
    KR100308101B1|2001-11-30|Semiconductor device and its manufacturing method
    US7741198B2|2010-06-22|Method for fabricating a probing pad of an integrated circuit chip
    US20060024951A1|2006-02-02|Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer
    US9165883B2|2015-10-20|Interconnection structure for an integrated circuit
    US7309654B2|2007-12-18|Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics
    US6518643B2|2003-02-11|Tri-layer dielectric fuse cap for laser deletion
    JP4037561B2|2008-01-23|Manufacturing method of semiconductor device
    US6858511B1|2005-02-22|Method of semiconductor via testing
    JP2005072384A|2005-03-17|Method for manufacturing electronic device
    同族专利:
    公开号 | 公开日
    CN1204149A|1999-01-06|
    US6225227B1|2001-05-01|
    JP2967755B2|1999-10-25|
    CN1118870C|2003-08-20|
    JPH10294347A|1998-11-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-04-17|Priority to JP9100353A
    1997-04-17|Priority to JP97-100353
    1998-04-17|Application filed by 가네코히사시, 닛폰덴키(주)
    1998-11-25|Publication of KR19980081493A
    2002-06-26|Application granted
    2002-06-26|Publication of KR100325499B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP9100353A|JP2967755B2|1997-04-17|1997-04-17|Method for manufacturing semiconductor device|
    JP97-100353|1997-04-17|
    [返回顶部]